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26301.102j description the a3935 is designed specifically for automotive applications that require high-power motors. each provides six high-current gate drive outputs capable of driving a wide range of n-channel power mosfets. a requirement of automotive systems is steady operation over a varying battery input range. the a3935 integrates a pulse- frequency modulated boost converter to create a constant supply voltage for driving the external mosfets. bootstrap capacitors are utilized to provide the above battery supply voltage required for n-channel fets. direct control of each gate output is possible via six ttl- compatible inputs. a differential amplifier is integrated to allow accurate measurement of the current in the three-phase bridge. diagnostic outputs can be continuously monitored to protect the driver from short-to-battery, short-to-supply, bridge-open, and battery under/overvoltage conditions. additional protection features include dead-time, vdd undervoltage, and thermal shutdown. the a3935 is supplied in a 36-lead 0.8 mm pitch qsop (package lq, similar to soicw). the lead (pb) free variants (suffix ?t ) have 100% matte tin leadframe plating. features and benefits ? drives wide range of n-channel mosfets in 3-phase bridges ? pfm boost converter for use with low-voltage battery supplies ? internal ldo regulator for gate-driver supply ? bootstrap circuits for high-side gate drivers ? current monitor output ? adjustable battery overvoltage detection ? diagnostic outputs ? motor lead short-to-battery, short-to-ground, and bridge- open protection ? undervoltage protection ? ?40c to 150c t j operation ? thermal shutdown 3-phase power mosfet controller for automotive applications package 36-pin qsop (lq): typical application approximate scale 1:1 a3935
3-phase power mosfet controller for automotive applications a3935 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com selection guide absolute maximum ratings part number pb-free packing terminals package a3935klqtr 1 ? 1500 pieces/reel 36 qsop (similar to soicw) surface mount A3935KLQTR-T 2 yes 1 variant has been determined to be obsolete and is no longer in production. status change: october 31, 2011. 2 variant is in production but has been determined to be not for new design. this classification indicates that sale of the variant is currently restricted to existing customer applications. the variant should not be purchased for new design applications because obsolescence in the near future is probable. samples are no longer available. status change: october 31, 2011. parameter symbol conditions rating units load supply voltage v bat vbat pin ?0.6 to 40 v v drain vdrain pin v boost vboost pin v boostd vboostd pin output voltage range v gh x gha, ghb, and ghc pins ?4 to 55 v v s x sa, sb, and sc pins ?4 to 40 v v gl x gla, glb, and glc pins ?4 to 16 v v c x ca, cb, and cc pins ?0.6 to 55 v sense circuit voltage v cs x csn and csp pins ?4 to 6.5 v v lss lss pin logic supply voltage v dd vdd pin ?0.3 to 6.5 v logic input/output v ovset ovset pin v boosts boosts pin v csout csout pin v dsth vdsth pin remaining logic pins esd rating ? human body model aec-q100-002; all pins 2.5 kv esd rating ? charged device model aec-q100-011; all pins 1050 v operating temperature t a range k ?40 to 135 c junction temperature* t j(max) fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. these condi- tions can be tolerated, but should be avoided. 150 c storage temperature range t stg ?55 to 150 c
3-phase power mosfet controller for automotive applications a3935 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com vreg high-side driver low-side driver turn on delay ca phase a gha sa gla lss csn to p h a s e b c boot to p h a s e c turn on delay r s vboost vbat control logic csp boosts boostd ahi alo bhi blo chi clo enable gnd cs drain-source fault monitor vbat overvoltage vbat undervoltage vreg undervoltage short to ground short to battery bridge open vdd undervoltage thermal shutdown vdsth sa sb sc csout vdrain low drop out linear regulator vreg refi refv lss vdrain (kelvin) fa ult motor supply voltage uvflt ovflt ovset vdd vbat vign vbat vreg vdd vdd external +5v os (blank) os (off) dwg. fp-053 functional block diagram
3-phase power mosfet controller for automotive applications a3935 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics at t j = ?40c to 150c, v bat = 7 to 16 v, v dd = 4.75 to 5.25 v, enable = 22.5 khz, 50% duty cycle, two phases active;unless otherwise noted characteristics symbol conditions min. typ 1 . max. units power supply v dd supply current i dd all logic inputs = 0 v ? ? 7.0 ma v bat supply current i bat all logic inputs = 0 v ? ? 3.0 ma battery voltage operating range v bat 7.0 ? 40 v bootstrap diode forward voltage v dboot i dboot = ?i cx = 10 ma, v dboot = v reg ? v c x 0.8 ? 2.0 v i dboot = ?i cx = 100 ma 1.5 ? 2.3 v bootstrap diode resistance r dboot r dboot (100 ma) = (v dboot (150 ma) ? v dboot (50 ma)) / 100 ma 2.5 ? 7.5 bootstrap diode current limit 2 i dm 3 v < v reg ? v c x < 12 v ?150 ? ?1150 ma bootstrap quiescent current i cx v cx = 40 v, ghx = on 10 ? 30 a bootstrap refresh time t refresh v sx = low, to guarantee v = +0.5 v refresh of 0.47 f bootstrap capacitor, cboot, to v cx ? v sx = +10 v ? ? 2.0 s vreg output voltage 3 v reg v bat = 7 to 40 v, v boost from boost regulator 12.7 ? 14 v vreg dropout voltage 4 v regdo v regdo = v boost ? v reg , i reg = 40 ma ? 0.9 ? v gate drive average supply current i reg no external dc load at vreg, c reg = 10 f??40ma vreg input bias current i regbias current into v boost , enable = 0 ? ? 4.0 ma boost supply vboost output voltage limit v boostm v bat = 7 v 14.9 ? 16.3 v vboost output voltage limit hysteresis ? v boostm 35 ? 180 mv boost switch on resistance r ds(on) i boostd < 300 ma ? 1.4 3.3 boost switch maximum current i boostsw ? ? 300 ma boost current limit threshold voltage v bi(th) increasing v boosts 0.45 ? 0.55 v off time t off 3.0 ? 8.0 s blanking time t blank 100 ? 220 ns control logic logic input voltage v i(1) minimum high level input for logic 1 2.0 ? ? v v i(0) maximum low level input for logic 0 ? ? 0.8 v logic input current i i(1) v i = v dd ? ? 500 a i i(0) v i = 0.8 v 50 ? ? a logic input hysteresis v ihys 100 ? 300 mv logic output high voltage v o(h) i o(h) = ?800 a v dd ? 0.8 ?? v logic output low voltage v o(l) i o(l) = 1.6 ma ? ? 0.4 v gate drives, gh x (internal source, or upper, switch stages) 5 output high voltage v dsl(h) ghx: i xu = ?10 ma, v sx = 0 v reg ? 2.26 ?v reg v glx: i xu = ?10 ma, v lss = 0 v reg ? 0.26 ?v reg v source current (pulsed) i xu v sdu = 10 v, t j = 25c ? 800 ? ma v sdu = 10 v, t j = 135c 400 ? ? ma source on resistance r sdu(on) i xu = ?150 ma, t j = 25c 4.0 ? 10 i xu = ?150 ma, t j = 135c 7.0 ? 15 continued on the next page?
3-phase power mosfet controller for automotive applications a3935 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics (continued) at t j = ?40c to 150c, v bat = 7 to 16 v, v dd = 4.75 to 5.25 v, enable = 22.5 khz, 50% duty cycle, two phases active;unless otherwise noted characteristics symbol conditions min. typ 1 . max. units gate drives, gl x (internal sink or lower switch stages) 6 sink current (pulsed) i xl v dsl = 10 v, t j = 25c ? 850 ? ma v dsl = 10 v, t j = 135c 550 ? ? ma sink on resistance r dsl(on) i xl = 150 ma, t j = 25c 1.8 ? 6.0 i xl = 150 ma, t j = 135c 3.0 ? 7.5 gate drives, gh x , gl x (general) 5,6 propagation delay, logic only t pd logic input to unloaded gh x , gl x ? ? 150 ns output skew time t sk(o) grouped by edge, phase?to?phase ? ? 50 ns dead time (shoot?through prevention) t dead between gh x , gl x transitions of same phase 75 ? 180 ns sense amplifier input bias current 2 i bias csp = csn = 0 v ?180 ? ?360 a input offset current 2 i io csp = csn = 0 v ? ? 35 a input resistance r i csp with respect to gnd ? 80 ? k csn with respect to gnd ? 4.0 ? k diff. input operating voltage v id v id = csp ? csn, ?1.3v < csp,n < 4v ? ? 200 mv output offset voltage v oo csp = csn = 0 v 77 250 450 mv output offset voltage drift v oo csp = csn = 0 v ? 100 ? v/c input common mode operating range v ic csp = csn ?1.5 ? 4.0 v voltage gain a v v id = 40 to 200 mv 18.6 19.2 19.8 v/v low output voltage error e v v id = 0 to 40 mv, v o = (19.2 v id ) + v o + e v ? ? 25 mv dc common mode attenuation a v c csp = csn = 200 mv 28 ? ? db output resistance r o v csout = 2.0 v ? 8.0 ? output dynamic range v csout i csout = ?100 a at top rail, 100 a at bottom rail 0.075 ? v dd ? 0.25 v output current, sink i sink v csout = 2.5 v 20 ? ? ma output current, source 2 i source v csout = 2.5 v ?1.0 ? ? ma vdd supply ripple rejection psrr vdd csp = csn = gnd, frequency = 0 to 1 mhz 20 ? ? db vreg supply ripple rejection psrr vreg csp = csn = gnd, frequency = 0 to 300 khz 45 ? ? db small signal 3 db bandwidth bw f3db 10 mv input ? 1.6 ? mhz ac common mode attenuation a v c(ac) v cm = 250 mv(pp), frequency = 0 to 800 khz 26 ? ? db output slew rate (positive or negative) sr 200 mv step input, measured at 10/90% points 10 ? ? v/ s fault logic vdd undervoltage v dd(uv) decreasing v dd 3.8 ? 4.3 v vdd undervoltage hysteresis ? v dd(uv) v dd(recovery) ? v dd(uv) 100 ? 300 mv ovset operating voltage range v set(ov) 0?v dd v ovset calibrated voltage range v set(ov)cal 0 ? 2.5 v ovset input current range 2 i set(ov) ?1.0 ? 1.0 a vbat overvoltage range v bat(ov) 0 v < v set(ov) < 2.5 v 19.4 ? 40 v increasing v bat , v set(ov) = 0 v 19.4 22.4 25.4 v vbat overvoltage hysteresis ? v bat(ov) percent of v bat(ov) value set by v set(ov) 9.0 ? 15 % continued on the next page?
3-phase power mosfet controller for automotive applications a3935 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics (continued) at t j = ?40c to 150c, v bat = 7 to 16 v, v dd = 4.75 to 5.25 v, enable = 22.5 khz, 50% duty cycle, two phases active;unless otherwise noted characteristics symbol conditions min. typ 1 . max. units vbat overvoltage gain constant k bat(ov) v bat(ov) = (k bat(ov) x v set(ov) ) + v bat(ov) (0); v bat(ov)(0) at v set(ov) = 0 ? 12 ? v/v vbat undervoltage v bat(uv) decreasing v bat 5.0 5.25 5.5 v vbat undervoltage hysteresis v bat(uv) percent of v bat(uv) 8.0 ? 12 % vreg undervoltage v reg(uv) decreasing v reg 9.9 ? 11.1 v vdsth input range v dsth 0.5 ? 3.0 v vdsth input current i dsth v dsth > 0.8 v 40 ? 100 a short?to?ground threshold v stg(th) with a high?side driver on, as v sx decreases, v drain ? v s x > v stg causes a fault v dsth ? 0.3 ? v dsth + 0.2 v short?to?battery threshold v stb(th) with a low?side driver on, as v sx increases, v s x ? v lss > v stb causes a fault v dsth ? 0.3 ? v dsth + 0.2 v vdrain-open bridge operating range v drain 7 v < v bat < 40 v ?0.3 ? v bat + 2.0 v vdrain - open bridge current i vdrain 7 v < v bat < 40 v 0 ? 1.0 ma vdrain /open bridge threshold voltage v bdgo(th) if v drain < v bdgoth then a bridge fault occurs 1.0 ? 3.0 v thermal shut down temperature t j 160 170 180 c thermal shutdown hysteresis ? t j 7.0 10 13 c 1 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. 2 negative current is defined as coming out of (sourcing) the specified device terminal. 3 for v boostm < v boost < 40 v power dissipation in the v reg ldo increases. observe t j < 150c limit. 4 with v boost decreasing, dropout voltage measured at v reg = v reg(ref) ? 200 mv where v reg(ref) = v reg at v boost = 16 v. 5 for gh x : v sdu = v c x ? v gh x , v dsl = v gh x ? v s x , v dsl(h) = v c x ? v sdu ? v s x . 6 for gl x : v sdu = v reg ? v gl x , v dsl = v gl x ? v lss , v dsl(h) = v reg ? v sdu ? v lss.
3-phase power mosfet controller for automotive applications a3935 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com characteristic symbol test conditions* value units package thermal resistance r ja on 4-layer pcb, based on jedec standard 44 oc/w *additional thermal information available on allegro web site. thermal characteristics 50 75 100 125 150 25 allowable package power dissipation in watts ambient temperature in c 5.0 0 1.0 2.0 3.0 4.0 r ja = 44c/w* power dissipation versus ambient temperature
3-phase power mosfet controller for automotive applications a3935 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com terminal descriptions ahi, bhi, and chi. direct control of high-side gate outputs gha, ghb, and ghc. logic 1 drives the gate on. logic 0 pulls the gate down, turning off the external power mosfet. inter- nally pulled down when the terminal is open. alo, blo, and clo. direct control of low-side gate outputs gha, ghb, and ghc. logic 1 drives the gate on. logic 0 pulls the gate down, turning off the external power mosfet . inter- nally pulled down when the terminal is open. boostd. boost converter switch drain connection . boosts. boost converter switch source connection. ca, cb, and cc. high-side connection for the bootstrap capacitors, cboot x , positive supply for high-side gate drive. the bootstrap capacitor is charged to v reg when the output s x terminal is low. when the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for n-channel power mosfets. csn. input for current-sense differential amplifier, on the inverting, negative side. kelvin connection for the ground side of the current-sense resistor, rsense. csout. amplifier output voltage proportional to the current sensed across an external low-value resistor placed in the ground side of the power mosfet bridge. csp. input for current-sense differential amplifier, on the non- inverting, positive side. connected to the positive side of the sense resistor, rsense. enable. logic 0 disables the gate control signals and switches off all the gate drivers (low) causing a coast condition. can be used in conjunction with the gate inputs to pwm (pulse wave modulate) the load current. internally pulled down when the terminal is open. f a u l t . diagnostic logic output signal. when low, indicates that one or more fault conditions have occurred. gha, ghb, and ghc. high-side gate drive outputs for n-channel mosfet drivers. external series gate resistors can control the slew rate seen at the power driver gate, thereby controlling the di / dt and dv / dt of s x outputs. gla, glb, and glc. low-side gate drive outputs for external, n-channel mosfet drivers. external series gate resistors can control slew rate. gnd. ground, or negative, side of vdd and vbat supplies. lss. low-side gate driver return. connects to the common sources on the low sides of the power mosfet bridge. ovflt. logic 1 indicates that the v bat level exceeded the vbat overvoltage trip point set by the ovset level. it will recover after exceeding a hysteresis below that maximum value. normally, it has a high-impedance state. if ovflt and uvflt are both in high-impedance state; then, at least, a thermal shutdown or vdd undervoltage has occurred. ovset. a positive dc level that controls the vbat overvoltage trip point. usually, set by a precision resistor divider network between vdd and gnd, but can be held grounded for a preset value. when this terminal is open, it sets an unspecified but high overvoltage trip point. sa, sb, and sc. directly connected to the motor terminals, these terminals sense the voltages switched across the load and are connected to the negative side of the bootstrap capacitors, cboot x . also, are the negative supply connection for the floating high-side drivers. uvflt. logic 1 indicates that the v bat level is below its minimum value. it will recover after exceeding a hysteresis above that minimum value. has a high-impedance state. if uvflt and ovflt are both in high-impedance state; then, at least, a thermal shutdown or vdd undervoltage has occurred. vbat. battery voltage. positive input. usually connected to the motor voltage supply. vboost. boost converter output, 16 v nominal, is also the input to the regulator for vreg. has internal boost-current and boost-voltage control loops. in high-voltage systems is approximately one diode drop below v bat . vdd. logic supply, +5 v nominal. vdrain. kelvin connection for drain-to-source voltage monitor. connected to the high-side drains of the mosfet bridge. high impedance when this terminal is open, and registers as a short-to- ground fault on all motor phases. vdsth. a positive dc level that sets the drain-to-source monitor threshold voltage. internally pulled down when this terminal is open. vreg. high-side gate driver supply, 13.5 v nominal. has low- voltage dropout (ldo) feature.
3-phase power mosfet controller for automotive applications a3935 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com motor lead protection. a fault detection circuit monitors the voltage across the drain-to-source of the external mosfets. a fault is asserted low on the output terminal, f a u l t , if the drain-to-source voltage of any mosfet that is instructed to turn on is greater than the voltage applied to the v dsth input terminal. when a high-side switch is turned on, the voltage from v drain to the appropriate motor phase output, v sx , is examined. if the motor lead is shorted to ground before the high-side is turned on, the measured voltage will exceed the threshold and the f a u l t terminal will go low. similarly, when a low-side mosfet is turned on, the differential voltage between the motor phase (drain) and the lss terminal (source) is monitored. v dsth is set by a resistor divider to v dd . the v drain is intended to be a kelvin connection for the high-side, drain-to-source monitor circuit. voltage drops across the power bus are eliminated by connecting an isolated pcb trace from the v drain terminal to the drain of the mosfet bridge. this allows improved accuracy in setting the v dsth threshold voltage. the low-side, drain-to-source monitor uses the lss terminal, rather than v drain , for comparison with v dsth . the a3935 just reports these motor faults. fault outputs. transient faults on any of the fault outputs are to be expected during switching, and will not disable the gate drive outputs. external circuitry or controller logic must determine if the faults represent a hazardous condition. f a u l t . this terminal will go active low when any of the follow- ing conditions occur: ? v bat overvoltage ? v bat undervoltage ? v reg undervoltage ? motor lead short-to-ground ? motor lead short-to-supply or short-to-battery ? bridge (or v drain ) open ? v dd undervoltage ? thermal shut down ovflt. asserts high when a v bat overvoltage fault occurs and resets low after a recovery hysteresis. it has a high-impedance state when a thermal shutdown or v dd undervoltage occurs. the voltage at the ovset terminal, v ovset , controls the v bat over- voltage set point v bat(ov) , as follows: v bat(ov) = ( a bat(ov) v set(ov) ) + v bat(ov)(0) , where a bat(ov) is the gain (12) and v bat(ov)(0) is the value of v bat(ov) when v set(ov) = 0 (v bat(ov) 22.4). for the above formula to be valid, all variables must be in range and below the maximum operating specification. uvflt. asserts high when a v bat undervoltage fault occurs and resets low after exceeding a recovery hysteresis. it has a high- impedance state when a thermal shut down or v dd undervoltage occurs. ovflt and uvflt are mutually exclusive by definition. current sensing. a current-sense amplifier is provided to allow system monitoring of the load current. the differential amplifier inputs are intended to be kelvin-connected across a low-value sense resistor or current shunt. the output voltage is represented by: v csout = ( i load a v r sense ) + v os where v os is the output voltage calibrated at zero load current and a v is the differential amplifier gain of about 19.2. if either the csp or csn pin is open, the csout pin will go to its maximum positive level. shut down. if a fault occurs because of excessive junction temperature or undervoltage on v dd or v bat , all gate driver outputs are driven low until the fault condition is removed. in addition, the boost supply switch and vreg are turned off until those undervoltages and junction temperatures recover. boost supply. v boost is controlled by an inner current- control loop, and by an outer voltage-feedback loop. the current-control loop turns off the boost switch for 5 s whenever the voltage across the boost current-sense resistor exceeds 500 mv. a diode reverse-recovery current flows through the sense resistor whenever the boost switch turns on, which could result in turning off the switch again if not for the blanking-time circuit. adjustment of this external sense resistor determines the maximum current in the inductor. whenever v boost exceeds the predefined threshold, 16 v nominal the boost switch is inhibited. functional description
3-phase power mosfet controller for automotive applications a3935 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com input logic table input output mode of operation enable x lo x hi gl x gh x 0 don?t care don?t care 0 0 all gate drive outputs low 10000 both gate drive outputs low 10101 high-side on 11010 low-side on 11100 xor circuitry prevents shoot-through fault response table operating conditions fault output regulator state driver output fault mode enable f a u l t ovflt uvflt boost v reg gh x gl x no fault don?t care 1 0 0 on on aa short-to-battery 1 b 000onon aa short-to-ground 1 c 000onon aa bridge (vdrain) fault 1 d 000onon aa vreg undervoltage don?t care 0 0 0 on on aa vbat overvoltage don?t care 0 1 0 off e on aa vbat undervoltage f don?t care 0 0 1 off off 0 0 vdd undervoltage f don?t care 0 high z high z off off 0 0 thermal shut down f don?t care 0 high z high z off off 0 0 a determined by input states: x lo, x hi, and enable. see input logic table. b short-to-battery can only be detected when the corresponding glx = 1. this fault is not detected when enable = 0. c short-to-ground can only be detected when the corresponding ghx = 1. this fault is not detected when enable = 0. d bridge fault appears as a short-to-ground fault on all motor phases. this fault is not detected when enable = 0. e off only because v boost v bat , which is above the voltage threshold of the boost regulator voltage control loop. f these faults are not only reported, but also action is taken by the internal logic to protect the a3935 and the system.
3-phase power mosfet controller for automotive applications a3935 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com number name function 1 csp current-sense input, positive-side 2 vdsth dc input, drain-to-source monitor threshold voltage 3 lss gate-drive source return, low-side 4 glc gate-drive c output, low-side 5 sc load phase c input 6 ghc gate-drive c output, high-side 7 cc bootstrap capacitor c 8 glb gate-drive b output, low-side 9 sb load phase b input 10 ghb gate-drive b output, high-side 11 cb bootstrap capacitor b 12 gla gate-drive a output, low-side 13 sa load phase a input 14 gha gate-drive a output, high-side 15 ca bootstrap capacitor a 16 vreg gate drive supply, positive 17 vdrain kelvin connection to mosfet high-side drains 18 vboost boost supply output number name function 19 boosts boost switch, source 20 boostd boost switch, drain 21 gnd ground, dc supply returns, negative 22 vbat battery supply, positive 23 uvflt vbat undervoltage fault output 24 ovflt vbat overvoltage fault output 25 f a u l t active-low fault output, primary 26 alo gate control input a, low-side 27 ahi gate control input a, high-side 28 bhi gate control input b, high-side 29 blo gate control input b, low-side 30 clo gate control input c, low-side 31 chi gate control input c, high-side 32 enable gate output enable 33 ovset dc input, overvoltage threshold setting for vbat 34 csout current-sense amplifier output 35 vdd logic supply, nominally +5 v 36 csn current-sense input, negative-side pin-out diagram cb gla sa gha ca vreg vdrain vboost alo fault ovflt uvflt vbat gnd boostd boosts 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 32 31 30 29 28 33 34 lss glc sc ghc cc glb sb ghb csout1 ovset enable chi clo blo bhi 2 1 35 36 23 22 21 20 19 24 25 26 27 csp vdsth csn vdd ahi terminal list
3-phase power mosfet controller for automotive applications a3935 12 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com package lq, 36-pin qsop c seating plane 15.30 0.10 10.31 0.30 7.50 0.10 0.20 0.10 2.64 max a 0.10 36x (0.36) 0.60 0.80 9.50 2.15 (0.80) 4 4 0.28 +0.05 ?0.04 0.84 +0.44 ?0.43 0.40 +0.12 ?0.11 2 1 36 gage plane seating plane a b b terminal #1 mark area a for reference only (qsop, nonjedec standard) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 sop80p1033x264-36m); adjust as necessary to meet application process requirements and pcb layout tolerances. all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances
3-phase power mosfet controller for automotive applications a3935 13 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com copyright ?2005-2011, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. j october 31, 2011 update product availability

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